Semiconductor integrated chips may utilize field effect transistors (FET's). FET'S, such as metal oxide semiconductor transistors, employ a gate dielectric film which is necessary for the switching operation of a transistor. Thermal oxide (e.g., SiO.sub.2) has long been the dominant dielectric material for FET's, very large scale integration (VLSI) and ultra large scale integration (ULSI). The excellent dielectric properties of thermal oxide allow manufacturers to consistently manufacture reliable integrated circuit (IC) chips that meet desired yield objectives.
Significant advancements in processing technologies of IC chips have continuously reduced the size of a unit transistor. Decreasing the size of transistors is sometimes referred to as technology scaling. The density of transistors has constantly increased from generation to generation of IC chips. The density of the IC chip is measured by the number of transistors or circuits which can be designed in a certain area of the IC chip. By reducing the size of single transistor, the operating speed of the FET is increased. Conversely, the time delay of the transistor or the time required to process an input command is decreased. The scaling of an FET results in reduction of both the lateral and vertical dimensions of the transistor. The scaling of the vertical dimensions leads to a reduction in the gate dielectric film thickness.
Within the past five years, technology scaling has increased the density of IC's by a factor of 2.5 or more, with a corresponding reduction of the gate dielectric film thickness by almost the same factor. For example, the gate dielectric film thickness of a typical FET has been reduced from about 12 nanometers to 5 nanometers.
Technology scaling has also dictated reductions in the operating voltage of an FET. The reduction in gate dielectric film thickness by a factor of about 2.5 over the past 5 years has been accompanied by reductions in the operating voltage (Vdd) by less than the factor of 2.5. Generally, the reduction in Vdd has not been directly proportional to the reduction in gate dielectric film thickness. As a result, the electric field strength across the gate dielectric film has increased. The yield and the reliability requirements for gate dielectric films are more difficult to meet because of the reduction in the gate dielectric film thickness and the resultant increase in electric field strength.
Reliable operation of the FET depends upon the reliability of the gate dielectric film. One measure of the gate dielectric film reliability is dielectric leakage current. The dielectric leakage current should be within established specifications under normal operating conditions and for the intended operating life time, typically 10 years of the product. If the gate dielectric film leakage is higher than the specification, the gate dielectric film is defective. Excessive gate dielectric film leakage is usually referred to as "dielectric breakdown" or "dielectric failure." Sometimes, the gate dielectric film is defective at the time of manufacture. Other failures occur during use.
The gate dielectric film should meet its yield and reliability objectives for the intended useful lifetime, under the specified operating voltage, temperature, and environmental conditions in accordance with all design implementation rules and guidelines. Design implementation rules vary for large area versus small area layout applications and for FET versus thin-oxide capacitor applications. Design guidelines include various product-test design mask levels.
Reliability testing of the gate dielectric film involves generation of accelerated life stress data to assess the product lifetime. Accelerated life stress testing degrades the gate dielectric film in a time-accelerated manner to produce measurable effects within a relatively short time. Testing of the gate dielectric film may require from less than one hour to over one year to produce the desired information for any given stress test condition. The time-acceleration of the degradation and breakdown mechanism is achieved by proper design of the parameters controlling the degradation and breakdown process. Typical test parameters are voltage and temperature.
The test and stress conditions normally exceed the intended conditions for normal use so that the mechanism of dielectric degradation/breakdown is temporally accelerated.
Usually, the technology reliability development activities employ a combination of test site vehicles, a cut version, a prototype of a product, or a specific design. The technology development test site normally contains several types of technology implementation guidelines and rules for the use of the gate dielectric material.
Information accumulated during technology development is integrated to define the physics and engineering models that govern the behavior and mechanism of dielectric film degradation and breakdown. The physics and engineering models are used for establishing the system and procedure through which routine monitoring of gate dielectric film integrity and reliability is maintained. A significant aspect of the routine monitoring of gate dielectric film reliability in manufacturing is the practicality, efficiency, and economy of routine testing for large manufacturing volumes. In contrast to initial technology development, routine monitoring of the manufacturing process for reliability should not require a protracted test period.
Prior art testing methods often destroy the gate dielectric film in the transistor by timing a time-to-breakdown of the dielectric. For example, Japanese Patent Application No. 08-046000 describes a destructive test resulting in dielectric breakdown. The test may require an extended time duration for the test to be completed because dielectric breakdown is required. A stress field is applied to the dielectric oxide. The total charge required to induce breakdown is measured just prior to breakdown of the oxide. The lifetime of the oxide for actual use conditions is estimated based on the total charge.
UK patent application GB 2 296 778A and Japanese patent application No. 08-023019 describe another destructive test resulting in dielectric breakdown. The test may require an extended period for execution. An initial current density is applied to the dielectric. The current density is increased in successive steps, or increased gradually as a function of time until dielectric breakdown is reached.
Other testing methods may not destroy the dielectric, but may induce permanent changes to the device characteristics. Japanese Patent JP 84109958, issued to F. Masumi and N. Hisatoshi, describes a test which changes the characteristics of the tested device. The test uses direct current and alternating current in accelerated stress measurements on Schottky gate FET's.
Other testing methods do not provide complete tests for gate dielectric film reliability. For example, U.S. Pat. No. 4,382,229 describes a reliability testing monitor limited to the channel hot-carrier mechanism. The gate current of an FET is measured as a function of time under accelerated stress conditions. Similarly, U.S. Pat. No. 5,615,377 describes a reliability test limited to the testing of channel hot carriers.
A need exists for a nondestructive test of gate dielectric film reliability, which is generally applicable to a wide variety of semiconductors. Furthermore, the need exists for a test that does not require a protracted test period and may be applied readily to monitor the manufacturing process.